1. Field of the Invention
The present invention relates generally to computer systems and, more particularly, to high frequency counters utilized in the performance analysis tests of Reduced Instruction Set Computer (RISC) systems.
2. Related Art
Conventionally, developers of computer systems have made use of hardware tools to conduct tests for analyzing various performance characteristics of a newly developed system. In particular, performance analysis tests are useful when developing a workstation, which can be defined as a computer system that is powerful enough to allow scientific and technical users to obtain the results they require. As this term is used, a workstation can be considered more powerful than the average personal computer that performs word processing and other general business applications, but less powerful than a mini-computer. These performance analyses provide valuable data for the developer to define and to isolate not only strong aspects of the system for exploitation in the marketplace, but also weak aspects of the system for future development and enhancement. Common tests to date include the delay time of the critical path and the number of MIPS (Million Instructions Per Second) that the system can typically provide.
Measuring performance is typically accomplished using either software or hardware tools. Measurements are typically corrupted using software tools because these tools must execute code that is extraneous to the source being measured. As a result, measurements using hardware are preferred because corruption from extraneous code execution is mitigated. However, measurements using hardware tend to be expensive.
The inventors use performance analysis tests in order to determine where a target system is spending its time during operation. This determination is used to fine tune poorly performing components of the target system. Fine tuning to increase poor performance is typically accomplished by modifying target system software or modifying the design of the next generation of the target system.
Although many performance analysis tests are available, the inventors realized that, especially with regard to the high frequency requirements of RISC systems, no tool offers a way of counting the maximum number of continuous cycles in which an event occurs.
Specifically, the inventors realized that no tools existed to count the number of times that the Interrupt bit (I-bit) was used by the CPU. Knowledge of this count would tell the users of the performance analysis tool how long interrupts were disabled during an event occurrence.
The inventors faced the problem of designing a counting solution that could be integrated with larger systems. In particular, they wanted to integrate a counting solution with state-of-the-art high frequency RISC based systems. As such, the inventors desired a counter that would operate in the high frequency environment of these systems.
They wanted a counter that counts the maximum number of continuous cycles that an event is true. However, prior to implementation, the inventors realized that designing a maximum event counter as described would have to be very fast, because current computer systems are performing at 50 Mhz (50,000,000 cycles/second) or faster. Consequently, this speed requirement would most likely mean using a lot of very expensive ECL-based hardware--which is expensive in terms of price, board space and power consumption.
One conventional approach for counting the maximum number of continuous cycles in which a system event occurs includes using a full speed counter in conjunction with a storage register which would be used to store the maximum value. With this alternative, the counter would count when the count enable (CE) goes true. Then, when CE goes false, the value of the counter would be compared to the value stored in the register. If the counter value is larger than the value in the register, then the counter value is stored in the register. Otherwise, if the counter value is less than or equal to the count value in the register, then the value in the register is saved and the counter value is cleared. Therefore, what essentially occurs is: (1) a count is recorded at the end of every string of count enables; (2) the largest of the two values--either the counter or the register--is saved. At the end of the desired time to be counted, the value in the register will be the maximum counting value. This conventional approach counts adequately, but has a few disadvantages.
One disadvantage with this conventional approach is the fact that a high speed path is necessary between the counter and the register. This path requires one high speed connection for each bit between the counter and the register.
Further, the particular design technology may allow the maximum value register to implement the input/output function by allowing the counter values to be loaded/unloaded serially. However, if this implementation is not allowed by the particular design technology, an additional register plus an additional data path to that register would be required.
In addition, a timing problem results from having to be able to perform the count, perform the comparison, transfer the value to the register and then clear the counter for a new count. As a result, a counter and register design could not operate as fast as an alternate design using the same level of technology.
Consequently, a strong need exists in the performance analysis industry for a way of counting the maximum/minimum number of continuous cycles in which a system event occurs that can meet the high frequency requirements of RISC systems.